`timescale 1ns / 10ps
`define clock_period 20

module counter_8bit_demo_tb;

	reg clk_50M;
	reg rst_n;
	wire tick;
	wire[7:0] count;

	counter_8bit_demo cnt0(
		.Clk_50M(clk_50M),
		.Rst_n(rst_n),
		.Tick(tick),
		.Count(count)
	);
	
	always #(`clock_period / 2) clk_50M = ~clk_50M;
	
	initial begin
	
		rst_n = 1'b0;
		#(`clock_period)
		rst_n = 1'b1;
		clk_50M = 1'b0;
		
		#(`clock_period * 50)
	
		$stop;
	
	end

endmodule
